KEYNOTE & PLENARY SPEAKERS
KEYNOTE SPEAKERS

Prof James C. M. Hwang
Cornell University, Ithaca, New York (USA)
Heterogeneous Integrated Sub-THz Transceiver Frontend
Heterogeneous integration of chiplets of different technologies on an interposer has been developed for digital and memory applications. Heterogenous integration for RF applications is just emerging. In this case, with few input/output channels, there is plenty of room in the bulk of the interposer for passives such as combiners, filters, duplexers, and antennas that are much more efficient than their thin-film counterparts. This makes it possible to have a complete RF frontend on an interposer. In particular, at millimeter-wave frequencies, substrate-integrated waveguides (SIWs) can have lower loss than microstrip or coplanar transmission lines. Further, with the signal fully enclosed in the SIW, transmit and receive channels can be placed next to each other without crosstalk. Thus, a linear phased array, with each transceiver narrower than a half wavelength, can be fabricated on the same interposer. In turn, the interposers can be stacked to form a 2D end-firing array. These points will be illustrated through the GaN-on-SiC technology. However, similar heterogeneous integration approaches are applicable to other device technologies and interposer materials.

Biography
James C. M. Hwang received the B.S. degree in physics from National Taiwan University, and the M.S. and Ph.D. degrees in materials science and engineering from Cornell University. He is currently a Professor at the Department of Materials Science and Engineering, Cornell University. Prior to that, he spent most of his academic career with Lehigh University, after years of industrial experience at IBM, Bell Labs, GE, and GAIN. He cofounded GAIN and QED; the latter became the public company IQE and remains the world’s largest compound-semiconductor epitaxial wafer supplier. He was a Consultant for the U.S. Air Force Research Laboratory, and a Program Officer for GHz-THz Electronics with the Air Force Office of Scientific Research. He was an IEEE Distinguished Microwave Lecturer. He is an IEEE Life Fellow and an Editor of IEEE Journal of Microwaves. He has worked for decades on electronic, optoelectronic, and micro-electromechanical materials, devices, and circuits. He was the recipient of many honors and awards, including the IEEE Lester F. Eastman Award for outstanding achievement in high-performance semiconductor devices. His current research focuses on sub-THz materials, devices, and circuits for next-generation automobile radars, Internet of Space, and 6G wireless communications.

Prof Aaron Voon-Yew Thean
National Univerisity of Singapore (NUS), Singapore
Towards Chips that Rewire Themselves? How Novel Material-System Co-Design can Enable Them
Ultra-low energy and area-efficient electronic systems are required to enable untethered computing at the edge of IoT. To realize self-learning edge-AI systems, conventional solely software-driven deep-learning neural networks becomes a major roadblock due the excessive energy expense of training. Hence, fundamental hardware change is likely needed. In this talk, we review our recent material innovations (E.g. Ferroelectric oxides and 2D Material) and we show how close coupling with new micro-architecture innovations (E.g. New memory physical layout and Monolithic 3D IC [1],[2](Fig.1(a)) may significantly accelerate in-memory computation. We explore wafer-level solution-processed CMOS-compatible use of 2D Material (MoS2/WSe2) [3](Fig.1(b)) to enable high-endurance memristors that can have properties superior to conventional oxide RRAMs. We discuss the use and enabling of multi-gated HZO-based low-thermal-budget ferroelectric oxide memory transistors for new reconfigurable non-volatile logic and interconnect [4] (Fig. 2(a)). In co-operation with specific system-level innovations, we review material-system co-design in data encoding for deep convolution neural network. We show through material-device-aware data encoding, error correction, and novel physical memory layout (staggered + Manhattan arrays) [1], that aim to simplify in-memory data processing, one can significantly manage variabilities while accelerating convolution deep neural network operations and offer substantial low-energy opportunities towards reconfigurable Edge-AI systems. Extending similar innovations to photonics, we show that new ferroelectric-lithium niobate integration can enable reconfigurable photonics and in-memory compute for photonics [5] (Fig. 2(b)).

Fig. 1: (a) Left: Oxide ReRAM for in-memory analog vector-matrix multiplication, Center: Novel 2D stair-case ReRAM array to accelerate convolution computation for CNN [1], Right: a proposed 3D staggered array for high-throughput in-memory CNN computation [2]. (b) 3D-Stacked Analog ReRAM device with solution-processed MoS2 switching layers [3].

Fig. 2: (a) HZO-IGZO Dual-Gate Memtransistor and the transistor’s non-volatile ferroelectric memory switching characteristics, with proposed application for BEOL-integrated switch matrix for non-volatile FPGA [4]. (b) HZO-Lithium Niobate Micro Ring Resonator (MRR), Electro-Optic Modulator and Memory with non-volatile photonic memory operations and energy reduction gains with respect to thermal-modulated MRR. We proposed it as a non-volatile switch for reconfigurable photonic inter-chip let interconnect system [5].
Biography
Aaron Thean is the Globalfoundries Professor of Electrical and Computer Engineering at the National University of Singapore (NUS). He is also the Deputy President (Academic Affairs) and Provost at NUS. In addition to his administrative duties, he is also the Director of SHINE research center on Next-Generation Hybrid Electronics, where Heterogeneous Integration process and design are investigated to enable new system innovation by chip packaging and other additive processing. Prior to NUS, Aaron Thean was the Vice President of Logic Technologies at IMEC. Working with Semiconductor Industry leaders like Intel, TSMC, Samsung, Globalfoundries, Apple, and Sony, he directed the research and development of next-generation semiconductor technologies and emerging nano-device architectures. Prior to joining IMEC in 2011, he was with Qualcomm’s CDMA technologies in San Diego, California. Aaron and his group worked on Qualcomm’s 20nm and 16nm mobile System-On-Chip technologies. From 2007 to 2009, Aaron was with IBM, where he developed the 28-nm and 32-nm low-power bulk CMOS technology at IBM East Fishkill, New York. Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc. (Highest Honors), M.Sc., and Ph.D. degrees in Electrical Engineering (Edmund J. James Scholar). Recognised by Singapore’s National Research Foundation (NRF) to be a NRF Returning Singaporean Scientist, he returned to Singapore to pursue his career as an academic in 2016. He has co-authored over 300 technical papers in the areas of advanced microelectronics and holds more than 50 US patents. He is fellow of the US National Academy of Inventors and IEEE.

Chao Chen
General Manager & Shareholder
Suzhou Chuangjie Intelligent Technology Co., Ltd., China
Title of Talk
(To be confirmed soon)
Biography
Chao Chen is an experienced investor and technopreneur who has extensive experience of starting businesses and managing multiple aspects of different tech businesses. He has a bachelor’s and master’s degree in applied mathematics. He previously worked as a quantitative trader at a hedge fund and is currently the general manager and shareholder of Suzhou Chuangjie Intelligent Technology Co., Ltd, a director of Shenzhen Yushun Electronics Co., Ltd. (an A-share listed company, stock code SZ.002289), co-founder and director of Beijing Wanjie Data Technology Co., Ltd. (a national-level specialised and innovative enterprise, mainly engaged in artificial intelligence computing power and industry model services), and vice chairman of the Supercomputing and Intelligent Computing Professional Committee of the China Communications Industry Association.
