{"id":32,"date":"2025-11-05T05:23:28","date_gmt":"2025-11-05T05:23:28","guid":{"rendered":"https:\/\/ieee-icta.org\/?page_id=32"},"modified":"2026-06-06T01:37:53","modified_gmt":"2026-06-06T01:37:53","slug":"keynote-speakers","status":"publish","type":"page","link":"https:\/\/ieee-icta.org\/zh\/keynote-speakers\/","title":{"rendered":"\u4e3b\u9898\u6f14\u8bb2\u5609\u5bbe"},"content":{"rendered":"\t\t
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KEYNOTE & PLENARY SPEAKERS<\/h2>\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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KEYNOTE SPEAKERS<\/h3>\t\t\t\t<\/div>\n\t\t\t\t
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Prof James C. M. Hwang<\/h2>\t\t\t\t<\/div>\n\t\t\t\t
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Cornell University<\/strong>, Ithaca, New York (USA)<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Heterogeneous Integrated Sub-THz Transceiver Frontend<\/b><\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Heterogeneous integration of chiplets of different technologies on an interposer has been developed for digital and memory applications. Heterogenous integration for RF applications is just emerging. In this case, with few input\/output channels, there is plenty of room in the bulk of the interposer for passives such as combiners, filters, duplexers, and antennas that are much more efficient than their thin-film counterparts. This makes it possible to have a complete RF frontend\u00a0 <\/span>on an interposer. In particular, at millimeter-wave frequencies, substrate-integrated waveguides (SIWs) can have lower loss than microstrip or coplanar transmission lines. Further, with the signal fully enclosed in the SIW, transmit and receive channels can be placed next to each other without crosstalk. Thus, a linear phased array, with each transceiver narrower than a half wavelength, can be fabricated on the same interposer. In turn, the interposers can be stacked to form a 2D end-firing array. These points will be illustrated through the GaN-on-SiC technology. However, similar heterogeneous integration approaches are applicable to other device technologies and interposer materials.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Biography<\/b><\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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James C. M. Hwang received the B.S. degree in physics from National Taiwan University, and the M.S. and Ph.D. degrees in materials science and engineering from Cornell University. He is currently a Professor at the Department of Materials Science and Engineering, Cornell University. Prior to that, he spent most of his academic career with Lehigh University, after years of industrial experience at IBM, Bell Labs, GE, and GAIN. He cofounded GAIN and QED; the latter became the public company IQE and remains the world’s largest compound-semiconductor epitaxial wafer supplier. He was a Consultant for the U.S. Air Force Research Laboratory, and a Program Officer for GHz-THz Electronics with the Air Force Office of Scientific Research. He was an IEEE Distinguished Microwave Lecturer. He is an IEEE Life Fellow and an Editor of IEEE Journal of Microwaves. He has worked for decades on electronic, optoelectronic, and micro-electromechanical materials, devices, and circuits. He was the recipient of many honors and awards, including the IEEE Lester F. Eastman Award for outstanding achievement in high-performance semiconductor devices. His current research focuses on sub-THz materials, devices, and circuits for next-generation automobile radars, Internet of Space, and 6G wireless communications.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Prof Aaron Voon-Yew Thean<\/h2>\t\t\t\t<\/div>\n\t\t\t\t
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National Univerisity of Singapore (NUS)<\/strong>, Singapore<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Towards Chips that Rewire Themselves? How Novel Material-System Co-Design can Enable Them<\/b><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Ultra-low energy and area-efficient electronic systems are required to enable\u00a0untethered computing at the edge of IoT. To realize self-learning edge-AI systems, conventional solely software-driven deep-learning neural networks becomes a major roadblock due the excessive energy expense of training. Hence, fundamental hardware change is likely needed. In this talk, we review our recent material innovations (E.g. Ferroelectric oxides and 2D Material) and we show how close coupling with new micro-architecture innovations (E.g. New memory physical layout and Monolithic 3D IC [1],[2](Fig.1(a)) may significantly accelerate in-memory computation. We explore wafer-level solution-processed CMOS-compatible use of 2D Material (MoS2<\/sub><\/span>\/WSe2<\/sub><\/span>) [3](Fig.1(b)) to enable high-endurance memristors that can have properties superior to conventional oxide RRAMs.\u00a0 <\/span>We discuss the use and enabling of multi-gated HZO-based low-thermal-budget ferroelectric oxide memory transistors for new reconfigurable non-volatile logic and interconnect [4] (Fig. 2(a)). In co-operation with specific system-level innovations, we review material-system co-design in data encoding for deep convolution neural network. We show through material-device-aware data encoding, error correction, and novel physical memory layout (staggered + Manhattan arrays) [1], that aim to simplify in-memory data processing, one can significantly manage variabilities while accelerating convolution deep neural network operations and offer substantial low-energy opportunities towards reconfigurable Edge-AI systems. Extending similar innovations to photonics, we show that new ferroelectric-lithium niobate integration can enable reconfigurable photonics and in-memory compute for photonics [5] (Fig. 2(b)).<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Fig. 1: (a) Left: Oxide ReRAM for in-memory analog vector-matrix multiplication, Center: Novel 2D stair-case ReRAM array to accelerate convolution computation for CNN [1], Right: a proposed 3D staggered array for high-throughput in-memory CNN computation [2].\u00a0 <\/span>(b) 3D-Stacked Analog ReRAM device with solution-processed MoS2<\/sub><\/span> switching layers [3].<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Fig. 2: (a) HZO-IGZO Dual-Gate Memtransistor and the transistor\u2019s non-volatile ferroelectric memory switching characteristics, with proposed application for BEOL-integrated switch matrix for non-volatile FPGA [4].\u00a0 <\/span>(b) HZO-Lithium Niobate Micro Ring Resonator (MRR), Electro-Optic Modulator and Memory with non-volatile photonic memory operations and energy reduction gains with respect to thermal-modulated MRR. We proposed it as a non-volatile switch for reconfigurable photonic inter-chip let interconnect system [5].<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Biography<\/b><\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Aaron Thean is the Globalfoundries Professor of Electrical and Computer Engineering at the National University of Singapore (NUS). He is also the Deputy President (Academic Affairs) and Provost at NUS. In addition to his administrative duties, he is also the Director of SHINE research center on Next-Generation Hybrid Electronics, where Heterogeneous Integration process and design are investigated to enable new system innovation by chip packaging and other additive processing. Prior to NUS, Aaron Thean was the Vice President of Logic Technologies at IMEC. Working with Semiconductor Industry leaders like Intel, TSMC, Samsung, Globalfoundries, Apple, and Sony, he directed the research and development of next-generation semiconductor technologies and emerging nano-device architectures.\u00a0 Prior to joining IMEC in 2011, he was with Qualcomm\u2019s CDMA technologies in San Diego, California. Aaron and his group worked on Qualcomm\u2019s 20nm and 16nm mobile System-On-Chip technologies. From 2007 to 2009, Aaron was with IBM, where he developed the 28-nm and 32-nm low-power bulk CMOS technology at IBM East Fishkill, New York. Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc. (Highest Honors), M.Sc., and Ph.D. degrees in Electrical Engineering (Edmund J. James Scholar). Recognised by Singapore\u2019s National Research Foundation (NRF) to be a NRF Returning Singaporean Scientist, he returned to Singapore to pursue his career as an academic in 2016.\u00a0 <\/span>He has co-authored over 300 technical papers in the areas of advanced microelectronics and holds more than 50 US patents. He is fellow of the US National Academy of Inventors and IEEE.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Chao Chen (\u9648\u8d85)<\/h2>\t\t\t\t<\/div>\n\t\t\t\t
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General Manager & Shareholder<\/strong><\/em><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Suzhou Chuangjie Intelligent Technology Co., Ltd.<\/strong>, China<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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From Cloud to Edge: Building AI Computing Infrastructure for the Age of Embodied Intelligence<\/b><\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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The AI computing landscape is undergoing a fundamental shift \u2014 from centralized training to distributed inference, from data centers to robot bodies. This keynote draws on the speaker’s multi-faceted experience as an operator of large-scale intelligent computing centers and an investor in embodied AI robotics companies to examine the full spectrum of AI computing challenges, from cloud to edge to on-body.<\/div>
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The talk begins with lessons from building and operating intelligent computing centers at scale, addressing the system-level challenges \u2014 thermal management, power supply, network interconnection, and GPU utilization \u2014 that determine infrastructure success or failure. It then pivots to the emerging frontier of embodied intelligence, drawing on insights from the speaker’s investments in humanoid robotics, including LingShen Technology (a Tsinghua-origin embodied AI company) and TIEN Kung (China’s national humanoid robot innovation platform). These ventures reveal an entirely new set of IC demands: extreme power efficiency under 50W, sub-10ms real-time inference latency, heterogeneous multi-modal processing, and safety-critical reliability \u2014 all within a mobile form factor.<\/div>
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The talk presents a three-tier computing architecture (cloud\u2013edge\u2013on-body) for embodied AI and concludes with actionable recommendations for the IC design community: how to bridge the gap between today’s chips and the requirements of tomorrow’s intelligent machines.<\/div>
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Biography<\/b><\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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Chao Chen is General Manager of Suzhou Chuangjie Intelligent Technology Co., Ltd. and serves as Vice Chair of the Supercomputing and Intelligent Computing Committee of the China Computer Industry Association (CCIA). His career spans three distinct waves of computing: quantitative finance, AI infrastructure, and embodied intelligence.<\/div>
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Mr. Chen began his career in quantitative trading, where he built high-frequency computational systems in which microsecond-level latency directly translated to financial performance. This experience gave him a deep understanding of computing as a core production asset rather than an IT overhead.<\/div>
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He subsequently moved into the AI infrastructure space, building and operating large-scale intelligent computing centers equipped with tens of thousands of GPU accelerators. Through hands-on management of these facilities, he gained first-hand insight into the system-level challenges of thermal management, power delivery, and GPU utilization that define the economics of AI at scale.<\/div>
Today, Mr. Chen is an active investor in the embodied AI sector. His portfolio includes LingShen Technology (\u7075\u751f\u79d1\u6280), a Tsinghua University-origin company developing universal brain platforms and full-size humanoid robots deployed in smart manufacturing, healthcare, and data center inspection; and TIEN Kung (\u5929\u5de5), the Beijing Innovation Center of Humanoid Robotics backed by MIIT and the Beijing Municipality, known for pioneering open-source full-size humanoid robots with advanced whole-body dynamic control.<\/div>
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Through this unique combination of operational and investment experience \u2014 from optimizing compute in financial markets, to operating GPU clusters at national scale, to funding the robots that will carry AI into the physical world \u2014 Mr. Chen brings a practitioner’s perspective on what the IC industry must deliver to enable the next generation of intelligent machines.<\/div>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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CS Chua<\/h2>\t\t\t\t<\/div>\n\t\t\t\t
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President and Managing Director
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Infineon Technologies Asia Pacific Pte. Ltd.<\/strong>, Singapore<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t

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L4\/L5 Autonomous vehicles: requirements and challenges for ICs
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Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) technologies are reshaping the automotive industry, driven by increasing safety regulations, consumer expectations, and rapid progress in semiconductor and artificial intelligence capabilities. This keynote reviews current market trends across automation levels and analyzes segmentation from Level 1\/2 (driver assistance) to Level 2+\/3 (conditional automation) and Level 4\/5 (high and full automation). While L1\/L2 systems are now widely deployed, L2+\/L3 solutions are expanding through enhanced perception and supervised autonomy, and L4\/L5 development is accelerating in selected commercial and mobility applications.<\/p>

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We present an overview of modern ADAS\/AD architectures, highlighting the transition from distributed electronic control units toward centralised and zonal computing platforms. Surround sensing technologies\u2014including cameras, radars, lidars, and acoustic sensing\u2014are examined as complementary modalities enabling robust environmental perception under diverse operating conditions. The increasing importance of multi-sensor fusion and AI-driven perception engines is discussed, emphasising scalability and real-time processing requirements.<\/p>

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This keynote further analyses the implications of centralised high-performance computing, including high-bandwidth data routing, in-vehicle networking, and optimized energy supply and power distribution. System-level constraints such as cybersecurity protection, functional safety compliance, redundancy strategies, and fail-operational design are addressed as critical enablers for higher automation levels.<\/p>

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Finally, we explore key requirements and challenges for integrated circuits (ICs) supporting ADAS\/AD platforms, including computational density, power efficiency, thermal management, deterministic latency, safety certification, and long-term reliability. The convergence of sensing, computing, connectivity, and safety architectures demands highly integrated, scalable semiconductor solutions. This work provides a comprehensive perspective on architectural evolution and technology enablers shaping the next generation of intelligent vehicles.<\/p>

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