Oct. 23
Presentaion: A pseudo-direct LiDAR system using charge-domain time-compressive CMOS image sensors
Abstract:
A virtually direct LiDAR system based on an indirect ToF image sensor and charge-domain temporal compressive sensing combined with deep learning is demonstrated. This scheme has high spatio-temporal sampling efficiency and offers advantages such as high pixel count, high photon-rate tolerance, immunity to multipath interference, constant power consumption regardless of incident photon rates, and motion artifact-free. The importance of increasing the number of taps of the charge modulator is suggested by simulation.
SPEAKER: Prof. Keiichiro Kagawa
Shizuoka University
BIO:
Keiichiro Kagawa received the Ph.D. degree in engineering from Osaka University, Osaka, Japan, in 2001.
In 2001, he joined Graduate School of Materials Science, Nara Institute of Science and Technology as an Assistant Professor. In 2007, he joined Graduate School of Information Science, Osaka University as an Associate Professor. In 2011, he joined Shizuoka University as an Associate Professor.
Since 2020, he has been a Professor with Shizuoka University, Hamamatsu, Japan. His research interests cover high-performance computational CMOS image sensors, imaging systems, and biomedical applications.
Oct. 23
Presentaion: Machine Learning for the Design of MEMS Devices
SPEAKER: Prof. Michael Kraft
University of Leuven
Abstract:
The presentation will first give a brief overview of the activities in micro- and nanosystems in the Electrical Engineering Department (ESAT) of KU Leuven, Belgium. It will describe the available infrastructure, especially the cleanroom housed in the Leuven Nanocentre. A short overview of current research projects in the division Micro- and Nanosystems (MNS) will be given, a research unit currently comprising around 30 researchers. Then, our research on Machine Learning (ML) for the design of MEMS devices will be described in more depth. Two demonstrators will be showcased: i) a MEMS accelerometer with a mechanical motion amplifier which was designed using an evolutionary algorithm. Compared to a conventional design we could achieve a 2.5-fold increase in the figure of merit comprising bandwidth and amplification ratio. The design is very different to a human-made, conventional design. An open-loop and a closed loop implementation will be shown. ii) A microgripper which again was designed with an evolutionary algorithm. We could demonstrate an almost 3-fold increase in the achieved deflection for a given actuation voltage with the machine learning algorithm compared to a standard design. Finally, an outlook will be given on ML for the design of resonators, which can be used for many different sensing applications.
BIO:
Michael Kraft is a full Professor of Micro- and Nanosystems at the University of Leuven, Department of Electrical Engineering in Belgium since 2017. He heads the Research Division Micro- and Nanosystems and is acting director of the Leuven Institute for Micro and Nanoscale Integration (LIMNI). He also is a guest professor at imec. Before joining KU Leuven, he was a professor at the University of Liege (2015-17) where he was responsible for the Microsys cleanroom. From 2012-2014, he was at the Fraunhofer Institute for Microelectronic Circuits and Systems in Duisburg, Germany, where he was Head of Department of Micro- and Nanosystems focussing on fully integrated microsensors and biohybrid systems. He concurrently held the W3 Professorial Chair of Integrated Micro- and Nanosystems at the University of Duisburg-Essen. From 1999 to 2012, he was a faculty member and Professor of Micro-System-Technology at the University of Southampton, UK. He graduated with a Dipl.-Ing. (Univ.) in electrical and electronics engineering at the Friedrich Alexander Universität Erlangen-Nürnberg in 1993. In 1997, he was awarded a PhD from Coventry University, UK on the development of a MEMS accelerometer. He then spent two years at the Berkeley Sensors and Actuator Centre at the University of California working on integrated MEMS gyroscopes. He has more than 25 years of experience in micro- and nano-fabrication techniques, microsensors and actuators and their interface circuits. He has a broad interest in MEMS and nanotechnology ranging from process development to system integration of MEMS and nano-devices. He has published over 300 peer reviewed journal and conference publications as an author or co-author. He also contributed to four textbooks on MEMS as author and editor. He has served on several steering and technical committees of international conferences such as Transducers, ISSCC, IEEE MEMS, IEEE Sensors, Eurosensors, MNE and MME, as well as being an associate editor for the IEEE Sensors Letter, IEEE JMEMS, IOP JMM, MDPI Sensors, and AMA Journal of Sensors and Sensors Systems.
Oct. 23
SPEAKER: Prof. Qiang Li
Hamburg University of Technology
Presentation:Frequency-Interleaving ADC Architecture for Timing Robustness
Abstract:
Gigahertz high-speed ADCs are highly demanded with the development of high-speed wireless, wireline and optical communication applications, where the time-interleaved architecture is commonly used with few other options. Time-interleaved ADCs, on the other hand, suffers from mismatch and timing errors among the interleaving channels. The timing errors, including sampling jitter, clock skew and bandwidth mismatch, are the fundamental limiting factor and increasingly difficult to be dealt with, especially for sampling rates up to tens to hundreds GHz, resulting in significant amount of design effort, complexity, and overhead in power and area. This work demonstrated a frequency-interleaved ADC architecture with a DAC-embedded 8-point AFT. The frequency-interleaved structure ensures robustness to timing errors, thereby obviating the requirement for additional calibration circuits. The AFT-based frequency-interleaver is performed by the charge redistribution after sampling, where all caps are shared with the CDAC. Circuit implementation of irrational twiddle factors is proposed, which relaxes the critical matching requirement. The ADC prototype has been fabricated in a 28nm CMOS technology, achieving 10b 13GS/s with 45.8dB SNDR and 56.1dB SFDR at Nyquist.
BIO:
Prof. Qiang Li is currently a Professor and Head of the Institute of Integrated Circuits and Systems at Hamburg University of Technology (TUHH), Germany, since 2025. Prior to this, he served as Professor and the Founding Head of the same institute at the University of Electronic Science and Technology of China (UESTC) in Chengdu from 2014 to 2025. From 2011 to 2014, he was an Associate Professor at Aarhus University, Denmark. He also held a professorship at UESTC from 2009 to 2011.
His industry experience includes serving as a Technical Consultant (Staff Design Engineer) at OKI Techno Centre in Singapore (2008–2009), and as an Engineer/Senior Engineer at the Institute of Microelectronics (IME), A*STAR, Singapore (2006–2008). He began his research career as a PhD student and Graduate Researcher at Nanyang Technological University (NTU), Singapore (2003–2006), after working as an Analog/Mixed-Signal IC Design Engineer at the Centre for Wireless Communications (CWC), Singapore (2001–2002).
He holds a Bachelor's degree in Electrical Engineering from Huazhong University of Science and Technology (HUST), China, obtained in 2001.
Oct. 23
SPEAKER: Prof. Zhiyi Yu
Sun Yat-sen University
Prensentaion: Low-Power Intelligent Computing Chips
Abstract:
Traditional CPU computing chips and currently mainstream GPU AI computing chips both face severe challenges in performance, power efficiency, and other aspects. This report will explore two key technologies and their applications in low-power intelligent computing chips: 1) Key technologies for streaming processor (GPU) chips based on in-memory-computation technology; 2) Circuit, architecture, and applications for brain-inspired computing chips based on asynchronous circuits.
BIO:
Zhiyi Yu received the B.S and M.S degrees from Fudan University and the Ph.D. degree from the University of California, Davis. Currently, he is a professor and the dean at the School of Microelectronics Science and Technology at Sun Yat-sen University, China.
His current research interests include microprocessor chip design and intelligent computing chip design. He has published over 150 papers, and has granted more than 50 patents. He served as the TPC chair/co-chair for several academic conferences such as ICTA, ICSICT, and APSIPA.
Oct. 24
SPEAKER: Prof. Jun Yang
Southeast University
Presentaion: Intelligent EDA--Empowering Solutions for All Circuit Challenges
Abstract:
As Stephen Wolfram stated in his TED talk, "The universe is running under a computational model." This report underscores the critical role of computation in integrated circuit (IC) design. It begins by outlining the current challenges faced by Large Language Models (LLMs) and then proposes corresponding solutions along with future development goals. To address common issues in chip design, the report introduces concepts such as a large-scale verification model supported by massive agents capable of incorporating human feedback, knowledge-driven automated analog circuit generation, and even the invention of novel circuit architectures.
BIO:
Jun Yang (Member, IEEE) received the B.S. and Ph.D. degrees in electronic engineering from Southeast University, Nanjing, China, in 1999 and 2004, respectively.,He is currently a Professor with the National ASIC System Engineering Research Center, Southeast University.
He has authored and coauthored over 50 technical articles in conferences and journals, including IEEE International Solid-State Circuits Conference (ISSCC), Design Automation Conference (DAC), the Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I: Regular Papers (TCASI), and IEEE Transactions on Very Large Scale Integration (TVLSI) Systems. He has authorized over 100 Chinese and U.S. invention patents. His current researches focus on SRAM design, in-memory computing, and near-threshold design.,Dr. Yang serves as an International Technical Program Committee member for ISSCC and ASSCC.(Based on document published on 16 October 2024).
